Lecture #15 – CPU Bus Structure
· Instruction Execution
To execute a machine instruction in the CPU, two phases are required:
1. Instruction Fetch
2. Instruction Execution
· Instruction Fetch
In a Von Neumann
architecture computer, the data and program are both stored in memory.
To execute the program, the CPU must retrieve the next machine
instruction and place it into the Instruction Register (IR).
The register transfer sequence for an instruction fetch generically
consists of:
1.
MAR ß PC
2.
Read Memory MBR =
M[ MAR ]
3.
IR ß MBR
4.
PC ß PC + 1
Thus for the CPU the
function, we need the following capabilities:
1.
transfer
the PC register to the MAR register
2.
read
memory contents into the MBR register
3.
transfer
the MBR register to the IR register
4.
add 1 to
the PC register
5.
transfer
ALU results to the PC register
We can already see that we need the ability
to transfer the PC register to multiple locations, including the MAR register
and to the Adder.
· Instruction Execution
Once an instruction is fetched into the IR register, the CPU must be capable of decoding it and performing the required functions.
If the instruction has an addressing mode (direct, indexed, indirect, or indexed-indirect), then the effective address must be calculated.
The following operations are required for effective address calculation:
Direct MAR ß IR0-7
Indexed MAR ß IR0-7
+ INDEX
Indirect MAR ß IR0-7
READ memory
MAR ß MBR
Index-Indirect MAR ß IR0-7
+ INDEX
READ memory
MAR ß MBR
From the address calculation we have new capability requirements:
6.
transfer
the IR register to the MAR register
7.
Add IR
register to INDEX registers
8.
transfer
ALU results to MAR register
9.
transfer
MBR register to MAR
Now for the actual instruction execution, the ASC instructions perform:
LDA READ memory
ACC ß MBR
STA MBR
ß ACC
WRITE
memory
ADD READ
memory
ACC
ß ACC + MBR
TCA ACC
ß ACC
ACC
ß ACC + 1
BRU PC ß MAR
BIP IF
ACC15 = 0 and ACC0-14 != 0 THEN
PC
ß MAR
BIN IF
ACC15 != 0 THEN
PC
ß MAR
SHL ACC1-15 ß
ACC0-14
ACC0
ß 0
SHR ACC0-14 ß
ACC1-15
LDX READ memory
INDEX ß MBR
STX MBR
ß INDEX
WRITE
memory
TIX INDEX
ß INDEX + 1
IF
INDEX = 0 THEN PC ß MAR
TDX INDEX
ß INDEX - 1
IF
INDEX != 0 THEN PC ß MAR
These finally finish our list of CPU requirements:
10.
transfer
MBR register to ACC register
11.
transfer
ACC register to MBR register
12.
add ACC
register and MBR register
13.
transfer
ALU results to ACC register
14.
complement
ACC register
15.
left
shift ACC register
16.
right
shift ACC register
17.
add one
to INDEX register
18.
subtract
one from INDEX register
19.
test
INDEX register for zero
20.
test ACC
register for positive
21.
test ACC
register for negative
22.
transfer
MAR register to PC register
There are many different ways to implement these requirements. The book uses a three bus design.
It is also quite feasible to implement these requirements using a one or two bus design. In these cases it will probably be necessary to add temporary registers to save results or inputs to the ALU.
With a three bus design the CPU requirements are straight forward. Notice that the CPU requirements determine which bus each register should be connected to. If the ALU is going to add two registers together, they must be on separate buses.
·
CPU
Structures:
The number of
buses connected to ALU determines bus architecture
Single-Bus
Structures
Ø 1 bus for whole system
Ø Slower, but cheaper than
multi-bus
Multi-Bus
Structures
Ø More than 1 bus
Ø Requires more complex hardware, but generally faster because more operations can be done simultaneously
·
Single Bus Structure
Example
: ADD with single bus
1. Y ß ACC
2. Z ß MBR + Y
3. ACC ß Z
·
Dual Bus Structure
Example : ADD with dual bus
1. Y ß ACC
2. ACC ß MBR + Y
·
Triple Bus Structure
Example:
ADD with triple bus
1. ACC ß ACC + MBR
With each new bus, the hardware becomes more complex but the number of operations is reduced. The number of temporary registers is also reduced.